Patent · US Active

Reducing color conflicts in triple patterning lithography

US9158885B1 · kind B1 · utility

36Cited by
4References
20Claims
0Family size

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Inventors

Key dates

Filing dateMay 15, 2014
Grant dateOct 13, 2015
Priority date
Expiry dateMay 15, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG03F7/70433
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

Methods of the present disclosure can include: using a computing device to perform actions including: applying a design rule check (DRC) on a proposed integrated circuit (IC) layout, wherein the DRC applies a set of restrictive design rules (RDRs) in response to the proposed IC layout being a contact area (CA) layout; computing a conflict graph for the proposed IC layout in response to one of the IC layout being a metal layer layout and the set of RDRs being satisfied; determining whether the IC layout is one of non-colorable, indeterminate, partially colorable, and fully colorable; and partially coloring the IC layout and identifying non-colorable nodes in response to the IC layout being indeterminate or partially colorable.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.