Plug via formation by patterned plating and polishing
US9159696B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2013 |
| Grant date | Oct 13, 2015 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. A via opening extends through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer. A mask on the top surface of the passivation layer includes a mask opening that is aligned with the via opening. A conductive layer is selectively formed in the via opening and the mask opening. The conductive layer projects above the top surface of the passivation layer. The method further includes planarizing the passivation layer and the conductive layer to define a plug in the via opening that is coupled with the metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.