Low noise semiconductor devices
US9171726B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2009 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jun 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices may be configured to reduce noise in the devices. For example, a semiconductor device may be configured or made with a first doped region within a semiconductor substrate to operate as an extended drain region, a trench isolation region, a second doped region between the first doped region and the trench isolation region, wherein the trench isolation region and the second doped region may be at least partially formed within the first doped region. Additionally, or alternatively, the second doped region may be within the first doped region and at least partially surround the trench isolation region, the first and second doped regions may have the same conductivity type, and the second doped region may have a higher conductivity than the first doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.