Alignment of integrated circuit chip stack

US9171742B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. 2 LLC · US

Inventors

• Evan G. Colgan · Chestnut Ridge, US
• Steven A. Cordes · Somers, US
• Daniel C. Edelstein · White Plains, US
• Vijayeshwar D. Khanna · Ossining, US
• Kenneth F. Latzko · Carmel, US
• Qinghuang Lin · Yorktown Heights, US
• Peter J. Sorce · Poughkeepsie, US
• Sri M. Sri-Jayantha · Ossining, US
• Robert L. Wisnieff · Ridgefield, US
• Roy R. Yu · Poughkeepsie, US

Key dates

• Filing date: Jul 22, 2013
• Grant date: Oct 27, 2015
• Expiry date: Jul 22, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/10156
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.