Isolation structure in gallium nitride devices and integrated circuits
US9171911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jul 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated semiconductor device which includes a substrate layer, a buffer layer formed on the substrate layer, a gallium nitride layer formed on the buffer layer, and a barrier layer formed on the gallium nitride layer. Ohmic contacts for a plurality of transistor devices are formed on the barrier layer. Specifically, a plurality of first ohmic contacts for the first transistor device are formed on a first portion of the surface of the barrier layer, and a plurality of second ohmic contacts for the second transistor device are formed on a second portion of the surface of the barrier layer. In addition, one or more gate structures formed on a third portion of the surface of the barrier between the first and second transistor devices. Preferably, the one or more gate structures and the spaces between the gate structures and the source contacts of the transistor devices collectively form an isolation region that electrically isolates the first transistor device from the second transistor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.