Balancing asymmetric spacers

US9177871B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Joachim Patzer · Rohrbach, DE
• Peter Baars · Dresden, DE
• Bastian Haussdoerfer · Dresden, DE

Key dates

• Filing date: Dec 30, 2013
• Grant date: Nov 3, 2015
• Expiry date: Jan 19, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0188
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.