Method of forming a semiconductor device employing an optical planarization layer

US9177874B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Joachim Patzer · Rohrbach, DE
• Ardechir Pakfar · Dresden, DE
• Dominic Thurmer · Dresden, DE
• Chih-Chun Wang · Hightstown, US
• Remi Riviere · Schweinhub, DE
• Robert Melzer · Radebeul, DE
• Bastian Haussdoerfer · Dresden, DE
• Martin Weisheit · Dresden, DE

Key dates

• Filing date: Aug 28, 2013
• Grant date: Nov 3, 2015
• Expiry date: Nov 5, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31144
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.