Vertical power MOSFET having planar channel and its method of fabrication
US9184248B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2015 |
| Grant date | Nov 10, 2015 |
| Priority date | — |
| Expiry date | Feb 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
A power MOSFET cell includes an N+ silicon substrate having a drain electrode. A low dopant concentration N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed and etched to have sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension next to the top portion of the sidewalls. A positive gate voltage inverts the lateral channel and increases the conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and extends virtually the entire length of the sidewalls. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.