Chip package with passives
US9190389B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2013 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Jul 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.