Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
US9190486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2012 |
| Grant date | Nov 17, 2015 |
| Priority date | — |
| Expiry date | Mar 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.