Xiuyu Cai
175Patents
18h-index
95Co-inventors
85Inventor score
Filing activity: Jan 16, 2012 → Sep 11, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8524592B1 | Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices | Electricity | 44 | Active |
| US8703557B1 | Methods of removing dummy fin structures when forming finFET devices | Electricity | 42 | Active |
| US9502518B2 | Multi-channel gate-all-around FET | Electricity | 40 | Active |
| US9455331B1 | Method and structure of forming controllable unmerged epitaxial material | Electricity | 34 | Active |
| US8541274B1 | Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed after source/drain formation | Electricity | 32 | Active |
| US9190260B1 | Topological method to build self-aligned MTJ without a mask | Electricity | 31 | Active |
| US9190486B2 | Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance | Electricity | 29 | Active |
| US9202920B1 | Methods for forming vertical and sharp junctions in finFET structures | Electricity | 25 | Active |
| US8921191B2 | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same | Electricity | 25 | Active |
| US9391200B2 | FinFETs having strained channels, and methods of fabricating finFETs having strained channels | Electricity | 24 | Active |
| US9748352B2 | Multi-channel gate-all-around FET | Electricity | 24 | Active |
| US9147748B1 | Methods of forming replacement spacer structures on semiconductor devices | Electricity | 24 | Active |
| US8835262B2 | Methods of forming bulk FinFET devices by performing a recessing process on liner materials to define different fin heights and FinFET devices with such recessed liner materials | Electricity | 21 | Active |
| US8753970B2 | Methods of forming semiconductor devices with self-aligned contacts and the resulting devices | Electricity | 21 | Active |
| US9070742B2 | FinFet integrated circuits with uniform fin height and methods for fabricating the same | Electricity | 20 | Active |
| US8841711B1 | Methods of increasing space for contact elements by using a sacrificial liner and the resulting device | Electricity | 20 | Active |
| US8551843B1 | Methods of forming CMOS semiconductor devices | Electricity | 20 | Active |
| US9082852B1 | LDMOS FinFET device using a long channel region and method of manufacture | Electricity | 19 | Active |
| US9064890B1 | Methods of forming isolation material on FinFET semiconductor devices and the resulting devices | Electricity | 16 | Active |
| US9153498B2 | Methods of forming semiconductor device with self-aligned contact elements and the resulting devices | Electricity | 15 | Active |
| US8815742B2 | Methods of forming bulk FinFET semiconductor devices by performing a liner recessing process to define fin heights and FinFET devices with such a recessed liner | Electricity | 15 | Active |
| US8580634B1 | Methods of forming 3-D semiconductor devices with a nanowire gate structure wherein the nanowire gate structure is formed prior to source/drain formation | Electricity | 14 | Active |
| US9281382B2 | Method for making semiconductor device with isolation pillars between adjacent semiconductor fins | Electricity | 14 | Active |
| US9337050B1 | Methods of forming fins for finFET semiconductor devices and the selective removal of such fins | Electricity | 13 | Active |
| US8941156B2 | Self-aligned dielectric isolation for FinFET devices | Electricity | 13 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.