Protective packaging for integrated circuit device
US9196557B1 · kind B1 · utility
1Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.