Patent · US Active

Semiconductor packaging arrangement

US9196577B2 · kind B2 · utility

1Cited by

7References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ralf Otremba · Kaufbeuren, DE
Josef Höglauer · Heimstetten, DE
Jürgen Schredl · Mering, DE
Xaver Schlögel · Sachsenkam, DE
Klaus Schiess · Allensbach, DE

Key dates

Filing date	Jan 9, 2014
Grant date	Nov 24, 2015
Priority date	—
Expiry date	May 19, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19107
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.