Method of generating test patterns for detecting small delay defects
US9201116B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2014 |
| Grant date | Dec 1, 2015 |
| Priority date | — |
| Expiry date | Aug 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318328
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of generating test patterns for testing a semiconductor processor for small delay defects (SDD) includes modifying interconnect delay values of interconnect paths by introducing values corresponding to (i) set-up and clock to Q delays of elements in the paths and (ii) latencies of associated clock networks. Critical nodes are selected and test patterns targeting the selected critical nodes are generated using timing slack resulting from the modified interconnect delays. A first selection of nodes that are critical in at-speed scan mode testing and a second selection of nodes that are critical in functional mode testing are made by static timing analysis (STA). Only the nodes featuring in both the first and second selections are selected for targeting small delay defects using at-speed scan test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.