Methods of forming transistors with retrograde wells in CMOS applications and the resulting device structures

US9209181B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Vara Govindeswara Reddy Vakada · Beacon, US
• Laegu Kang · Hopewell Junction, US
• Michael Ganz · Fishkill, US
• Yi Qi · Niskayuna, US
• Puneet Khanna · Beacon, US
• Srikanth B. Samavedam · Austin, US
• Sri Charan Vemula · Clifton Park, US
• Manfred Eller · Wappingers Falls, US

Key dates

• Filing date: Jun 14, 2013
• Grant date: Dec 8, 2015
• Expiry date: Oct 6, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/859

Abstract

A method includes forming a layer of silicon-carbon on an N-active region, performing a common deposition process to form a layer of a first semiconductor material on the layer of silicon-carbon and on the P-active region, masking the N-active region, forming a layer of a second semiconductor material on the first semiconductor material in the P-active region and forming N-type and P-type transistors. A device includes a layer of silicon-carbon positioned on an N-active region, a first layer of a first semiconductor positioned on the layer of silicon-carbon, a second layer of the first semiconductor material positioned on a P-active region, a layer of a second semiconductor material positioned on the second layer of the first semiconductor material, and N-type and P-type transistors.