Integrated circuit with matching threshold voltages and method for making same

US9214399B2 · kind B2 · utility

Assignee

• Efficient Power Conversion Corporation · US

Inventors

• Jianjun Cao · Torrance, US
• Robert Beach · Altadena, US
• Alexander Lidow · Manhattan Beach, US
• Alana Nakata · Redondo Beach, US
• Robert Strittmatter · Burbank, US
• Guangyuan Zhao · Torrance, US
• Yanping Ma · Torrance, US
• Chunhua Zhou · Suzhou, CN
• Seshadri Kolluri · San Jose, US
• Fang Liu · Toufen, TW
• Ming-Kun Chiang · Hsinchu, TW
• Jiali Cao · Torrance, US
• Agus Jauhar · Hsinchu, TW

Key dates

• Filing date: Jul 30, 2014
• Grant date: Dec 15, 2015
• Expiry date: Jul 30, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/111

Abstract

An integrated circuit having a substrate, a buffer layer formed over the substrate, a barrier layer formed over the buffer layer, and an isolation region that isolates an enhancement mode device from a depletion mode device. The integrated circuit further includes a first gate contact for the enhancement mode device that is disposed in one gate contact recess and a second gate contact for the depletion mode device that is disposed in a second gate contact recess.