Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits
US9214528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Jul 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an enhancement mode GaN HFET device with an isolation area that is self-aligned to a contact opening or metal mask window. Advantageously, the method does not require a dedicated isolation mask and the associated process steps, thus reducing manufacturing costs. The method includes providing an EPI structure including a substrate, a buffer layer a GaN layer and a barrier layer. A dielectric layer is formed over the barrier layer and openings are formed in the dielectric layer for device contact openings and an isolation contact opening. A metal layer is then formed over the dielectric layer and a photoresist film is deposited above each of the device contact openings. The metal layer is then etched to form a metal mask window above the isolation contact opening and the barrier and GaN layer are etched at the portion that is exposed by the isolation contact opening in the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.