Overlay performance for a fin field effect transistor device

US9219002B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Zhenyu Hu · Leonberg, DE
• Andy Wei · Queensbury, US
• Qi Zhang · State College, US
• Richard J. Carter · Los Altos, US
• Hongliang Shen · Ballston Lake, US
• Daniel T. Pham · Clifton Park, US
• Sruthi Muralidharan · Troy, US

Key dates

• Filing date: Sep 17, 2013
• Grant date: Dec 22, 2015
• Expiry date: Nov 2, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.