Transistors, semiconductor constructions, and methods of forming semiconductor constructions
US9219132B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Sep 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.