Methods of forming gate structures for FinFET devices and the resulting semiconductor products
US9219153B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 21, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Aug 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.