Structures and methods for making NAND flash memory
US9224475B2 · kind B2 · utility
2Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Aug 23, 2012 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell. Gaps etched through such openings may also define peripheral devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.