System for maintaining back gate threshold voltage in three dimensional NAND memory
US9230656B2 · kind B2 · utility
6Cited by
14References
20Claims
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Key dates
| Filing date | Jun 26, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.