Stacked integrated circuit package system
US9236319B2 · kind B2 · utility
4Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.