Method of introducing local stress in a semiconductor layer
US9240466B2 · kind B2 · utility
1Cited by
4References
23Claims
0Family size
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Key dates
| Filing date | Aug 4, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.