Methods of forming lateral and vertical FinFET devices and the resulting product
US9245885B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2015 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
Abstract
One illustrative method disclosed herein includes, among other things, forming first and second recessed gate structures, recessing the second recessed gate structure so as to define a further recessed second gate structure that exposes a channel structure within a gate cavity, forming first and second gate cap layers in first and second replacement gate cavities, respectively, forming a recess in the second gate cap layer that exposes the channel structure, forming a semiconductor material on the exposed portion of the channel structure within the recess in the second gate cap layer so as to define a first source/drain region for the vertical FinFET device, and forming various contact structures to the gates of the devices and the first source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.