Memory cell array structures and methods of forming the same
US9246100B2 · kind B2 · utility
4Cited by
12References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.