Semiconductor device and method of forming through mold hole with alignment and dimension control
US9252092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor die and an encapsulant formed over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A plurality of conductive vias is formed through the first insulating layer. A conductive pad is formed over the encapsulant. An interconnect structure is formed over the semiconductor die and encapsulant. A first opening is formed in the encapsulant to expose the conductive vias. The conductive vias form a conductive via array. The conductive via array is inspected through the first opening to measure a dimension of the first opening and determine a position of the first opening. The semiconductor device is adjusted based on a position of the conductive via array. A conductive material is formed in the first opening over the conductive via array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.