Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region
US9252172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jan 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.