Hierarchical asymmetric mesh with virtual routers
US9253085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2012 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Nov 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.