Mitigation of asymmetrical profile in self aligned patterning etch
US9257280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.