Low threshold voltage CMOS device
US9263344B2 · kind B2 · utility
4Cited by
0References
9Claims
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Key dates
| Filing date | Dec 9, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.