Fast mechanism for accessing 2n±1 interleaved memory system
US9268691B2 · kind B2 · utility
1Cited by
2References
24Claims
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Key dates
| Filing date | Jun 11, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/302
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n−1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.