Semiconductor device and method of land grid array packaging with bussing lines
US9269622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of making a semiconductor device is described. An embedded die panel comprising a plurality of semiconductor die separated by saw streets is provided. A conductive layer is formed by an electroless plating process, the conductive layer comprising bussing lines disposed in the saw streets and a redistribution layer (RDL) coupled to the semiconductor die and bussing lines. An insulating layer is formed over the conductive layer and embedded die panel, the insulating layer comprising openings disposed over the conductive layer outside a footprint of the semiconductor die. Interconnect structures are formed in the openings in the insulating layer by using the conductive layer as part of an electroplating process. The embedded die panel is singulated through the saw streets after forming the interconnect structures to remove the bussing lines and to from individual fan-out wafer level packages (FOWLPs).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.