Methods for testing integrated circuits of wafer and testing structures for integrated circuits
US9269642B2 · kind B2 · utility
1Cited by
15References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material over a first conductor material of the integrated circuit, and contacting a test probe to the deposited sacrificial material. The methods can also include testing the integrated circuit using the test probe contacting the sacrificial material. Finally, the methods can include removing the sacrificial material over the first conductor material of the integrated circuit subsequent to the testing of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.