Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
US9279192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02052
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict limitations are placed on any substrate that is to be processed in a chamber normally used for silicon substrates, so as to avoid contamination of the silicon wafers. To take full advantage of standard silicon processing equipment, the SiC substrates are of diameter of at least 150 mm. For proper growth of the SiC boule, the growth crucible is made to have interior volume that is six to twelve times the final growth volume of the boule. Also, the interior volume of the crucible is made to have height to width ratio of 0.8 to 4.0. Strict limits are placed on contamination, particles, and defects in each substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.