Controlling timing of negative charge injection to generate reliable negative bitline voltage
US9281030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2014 |
| Grant date | Mar 8, 2016 |
| Priority date | — |
| Expiry date | Mar 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to preventing or mitigating excessive drop in the negative voltage level of a bitline of memory bitcells by controlling the delay of a trigger signal for initiating injection of negative charge into the bitline. A write assist circuit causes negative charge to drop gradually in response to receiving a data input indicating a negative value of the bitline. When supply voltage is high, the timed delay of trigger signal is reduced, thereby causing negative charge to be injected into the bitline while bitline voltage remains at a higher voltage level and before the bitline voltage drops close to ground voltage. Since the negative charge is injected while the bitline voltage level is relatively high, the bitline is prevented from being pulled down to an excessively negative voltage level even when the supply voltage is relatively high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.