Patent · US Active

Chip scale packages and related methods

US9281258B1 · kind B1 · utility

4Cited by

0References

20Claims

0Family size

Assignee

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

Bih Wen Fon · Melaka City, MY
Soon Wei WANG · Seremban, MY
How Kiat Liew · Seri Kembangan, MY

Key dates

Filing date	Oct 30, 2014
Grant date	Mar 8, 2016
Priority date	—
Expiry date	Oct 30, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.