Patent · US Active

Method of fast analog layout migration

US9286433B2 · kind B2 · utility

0Cited by

7References

40Claims

0Family size

Assignees

Synopsys Taiwan Co., Ltd. · TW
SYNOPSYS, INC. · US

Inventors

Tung-Chieh Chen · Taipei, TW
Hung-Ming Chen · Zhubei City, TW
Yi-Peng Weng · Taipei, TW

Key dates

Filing date	Nov 18, 2013
Grant date	Mar 15, 2016
Priority date	—
Expiry date	Nov 18, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.