Method of reducing hot electron injection type of read disturb in dummy memory cells
US9286994B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Mar 26, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.