Stacked semiconductor die assemblies with thermal spacers and associated systems and methods
US9287240B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2013 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.