Method and structure for improving finFET with epitaxy source/drain
US9293459B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Sep 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed. The isolation structures obstruct lateral growth of a semiconductor material during a selective epitaxial grown process in formation of source/drain regions, thereby preventing merging of the source/drain regions at the ends of gate structures. As a result, a lateral distance between each sidewall of the gate material block and a corresponding outermost sidewall of an array of a plurality of semiconductor fins can be made sufficiently small without causing the electrical shorts of the source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.