Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US9293560B2 · kind B2 · utility
6Cited by
8References
8Claims
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Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Mar 22, 2016 |
| Priority date | — |
| Expiry date | Nov 5, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.