Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device

US9293587B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ajey Poovannummoottil Jacob · Watervliet, US
• Murat Kerem Akarvardar · Saratoga Springs, US

Key dates

• Filing date: Jul 23, 2013
• Grant date: Mar 22, 2016
• Expiry date: Oct 14, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).