In-line measurement of transistor device cut-off frequency
US9297853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2013 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Jun 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test circuit within a semiconductor wafer that measures a cut-off frequency for a transistor device under test may include a radio frequency source, located within a region of the wafer, that generates a radio frequency signal. A biasing circuit, also located within the region, may provide a current bias setting to the transistor device under test. The biasing circuit receives the radio frequency signal and applies a buffered radio frequency signal to the transistor device under test. The biasing circuit generates a buffered output signal based on the transistor device under test generating a first output signal in response to receiving the applied buffered radio frequency signal. An rf power detector, within the region, receives the first output signal and the radio frequency signal, and generates an output voltage signal, wherein the cut-off frequency of the transistor device under test is determined from the generated output voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.