Method of forming stressed SOI layer
US9305828B2 · kind B2 · utility
1Cited by
3References
25Claims
0Family size
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Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/324
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.