Air gap structure integration using a processing system
US9312168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an air gap structure in an integrated layer stack includes dry etching a mold layer disposed on the stack in a processing system under vacuum. The mold layer is disposed between one or more interconnects, and the process of dry etching of the mold layer exposes at least a portion of the interconnects. The method also includes depositing a liner layer over the exposed portion of the interconnects. In another embodiment, a method for forming an air gap structure in an integrated layer stack includes dry etching an oxide mold layer disposed on the stack in an a first processing chamber in a processing system under vacuum. The method also includes depositing a low-k material liner layer over the interconnects, wherein the liner has a thickness of less than about 2 nanometers. The methods disclosed herein are performed in a processing system without breaking vacuum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.