Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
US9318388B2 · kind B2 · utility
4Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2015 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.