Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
US9318404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Jun 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.