Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
US9318552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | May 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
Abstract
One illustrative method disclosed herein includes, among other things, forming a first epi semiconductor material in a source/drain region of a transistor device, the first epi semiconductor material having a first lateral width at an upper surface thereof, forming a second epi semiconductor material on the first epi semiconductor material and above at least a portion of one of a gate cap layer or one of the sidewall spacers of the device, wherein the second epi semiconductor material has a second lateral width at an upper surface thereof that is greater than the first lateral width, and forming a metal silicide region on the upper surface of the second epi semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.