Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness

US9330988B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Shawn A. Adderly · South Burlington, US
• Kyle Babinski · Swanton, US
• Daniel A. Delibac · Colchester, US
• David A. DeMuynck · Underhill, US
• Shawn R. Goddard · South Burlington, US
• Matthew D. Moon · Jeffersonville, US
• Melissa J. Roma · Bend, US
• Craig E. Schneider · Boise, US

Key dates

• Filing date: Dec 23, 2014
• Grant date: May 3, 2016
• Expiry date: Dec 23, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/12
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.